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MC10ELT25, MC100ELT25 -5V Differential ECL to TTL Translator
The MC10ELT/100ELT25 is a differential ECL to TTL translator. Because ECL levels are used, a +5 V, -5.2 V (or -4.5 V) and ground are required. The small outline 8-lead package and the single gate of the ELT25 makes it ideal for those applications where space, performance and low power are at a premium. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The 100 Series contains temperature compensation.
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8 1 SO-8 D SUFFIX CASE 751 8 1 TSSOP-8 DT SUFFIX CASE 948R 1 8 HLT25 ALYW 1 8 KLT25 ALYW
* * * * * * * * * * * *
2.6 ns Typical Propagation Delay 100 MHz FMAX CLK 24 mA TTL Outputs Flow Through Pinouts ESD Protection: >1 KV HBM, > 400 V MM Operating Range: VCC= 4.5 V to 5.5 V with GND= 0 V; VEE= -4.2 V to -5.7 V with GND= 0 V Internal Input Pulldown Resistors Q Output will default HIGH with inputs open or < 1.3 V Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34 Transistor Count = 38 devices VEE 1 D2 ECL D3 VBB 4 6 NC 8 VCC TTL 7 Q
8 HT25 ALYW 1
8 KT25 ALYW 1
H = MC10 K = MC100 A = Assembly Location
L = Wafer Lot Y = Year W = Work Week
*For additional information, see Application Note AND8002/D
ORDERING INFORMATION
Device MC10ELT25D MC10ELT25DR2 MC100ELT25D Package SO-8 SO-8 SO-8 SO-8 TSSOP-8 TSSOP-8 TSSOP-8 Shipping 98 Units/Rail 2500 Tape & Reel 98 Units/Rail 2500 Tape & Reel 98 Units/Rail 2500 Tape & Reel 98 Units/Rail 2500 Tape & Reel
5
GND
MC100ELT25DR2 MC10ELT25DT
Figure 1. 8-Lead Pinout and Logic Diagram (Top View) PIN DESCRIPTION
PIN D, D Q VBB VCC VEE GND NC FUNCTION ECL Differential Inputs TTL Output Reference Voltage Output Positive Supply Negative Supply Ground No Connect
MC10ELT25DTR2 MC100ELT25DT
MC100ELT25DTR2 TSSOP-8
(c) Semiconductor Components Industries, LLC, 2001
1
June, 2001 - Rev. 5
Publication Order Number: MC10ELT25/D
MC10ELT25, MC100ELT25
MAXIMUM RATINGS (Note 1)
Symbol VCC VEE VIN IBB TA Tstg JA JC JA JC Tsol Parameter Positive Power Supply Negative Power Supply Input Voltage VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Wave Solder 0 LFPM 500 LFPM std bd 0 LFPM 500 LFPM std bd <2 to 3 sec @ 248C 8 SOIC 8 SOIC 8 SOIC 8 TSSOP 8 TSSOP 8 TSSOP Condition 1 GND = 0 V GND = 0 V GND = 0 V Condition 2 VEE = -5.0 V VCC = +5.0 V Rating 7 -8 0 to VEE 0.5 -40 to +85 -65 to +150 190 130 41 to 44 185 140 41 to 44 5% 265 Units V V V mA C C C/W C/W C/W C/W C/W C/W C
1. Maximum Ratings are those values beyond which device damage may occur.
10ELT SERIES NECL DC CHARACTERISTICS VCC= 5.0 V; VEE= -5.0 V; GND= 0 V (Note 2)
-40C Symbol VIH VIL VBB VIHCMR IIH IIL Characteristic Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 3) Input HIGH Current Input LOW Current 0.5 Min -1230 -1950 -1.43 -2.8 Typ Max -890 -1500 -1.30 0.0 150 0.5 Min -1130 -1950 -1.35 -2.8 25C Typ Max -810 -1480 -1.25 0.0 150 0.3 Min -1060 -1950 -1.31 -2.8 85C Typ Max -720 -1445 -1.19 0.0 150 Unit mV mV V V A A
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 2. Input parameters vary 1:1 with GND. VEE can vary +0.06 V / -0.5 V. 3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with GND.
100ELT SERIES NECL DC CHARACTERISTICS VCC= 5.0 V; VEE= -5.0 V; GND= 0 V (Note 4)
-40C Symbol VIH VIL VBB VIHCMR IIH IIL Characteristic Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 5) Input HIGH Current Input LOW Current 0.5 Min -1165 -1810 -1.38 -2.8 Typ Max -880 -1475 -1.26 0.0 150 0.5 Min -1165 -1810 -1.38 -2.8 25C Typ Max -880 -1475 -1.26 0.0 150 0.5 Min -1165 -1810 -1.38 -2.8 85C Typ Max -880 -1475 -1.26 0.0 150 Unit mV mV V V A A
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 4. Input parameters vary 1:1 with GND. VEE can vary +0.8 V / -0.5 V. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with GND.
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MC10ELT25, MC100ELT25
TTL OUTPUT DC CHARACTERISTICS VCC = 4.5 V to 5.5 V; TA = -40C to +85C
Symbol VOH VOL ICCH ICCL IEE IOS Characteristic Output HIGH Voltage Output LOW Voltage Power Supply Current Power Supply Current Negative Power Supply Current Output Short Circuit Current -150 Condition IOH = -3.0 mA IOL = 24 mA 11 13 15 Min 2.4 0.5 16 18 21 -60 Typ Max Unit V V mA mA mA mA
AC CHARACTERISTICS VCC= 5.0 V; VEE= -5.0 V; GND= 0 V (Note 6 and Note 7)
-40C Symbol fmax tPLH tPHL tJITTER tr tf VPP Characteristic Maximum Toggle Frequency Propagation Delay @ 1.5 V Propagation Delay @ 1.5 V Cycle-to-Cycle Jitter Output Rise/Fall Times QTTL CL = 20 pF 10% - 90% CL = 20 pF Input Swing (Note 8) 200 1000 200 CL = 20 pF CL = 20 pF 1.7 2.6 TBD Min Typ 100 3.6 4.1 1.7 2.6 TBD 1.9 2.3 1000 200 1000 Max Min 25C Typ 100 3.6 4.1 1.7 2.6 TBD Max Min 85C Typ 100 3.6 4.1 Max Unit MHz ns ns ps ns mV
6. VCC can vary 0.25 V. VEE can vary +0.06 V / -0.5 V for 10ELT; VEE can vary +0.8 V / -0.5 V for 100ELT. 7. All loading with 500 ohms to GND, CL = 20 pF. 8. VPP(min) is the minimum input swing for which AC parameters are guaranteed. The device has a DC gain of 40.
Q TTL Driver
D TTL Receiver
CL * * 20 pF total cap AC load (includes fixture)
RL 500 W
GND
Figure 2. TTL Output Loading Used for Device Evaluation
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MC10ELT25, MC100ELT25
Resource Reference of Application Notes AN1404 - ECLinPS Circuit Performance at Non-Standard VIH Levels
AN1405 AN1406 AN1503 AN1504 AN1560 AN1568 AN1596 AN1650 AN1672 AND8001 AND8002 AND8020
- - - - - - - - - - - -
ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) ECLinPS I/O SPICE Modeling Kit Metastability and the ECLinPS Family Low Voltage ECLinPS SPICE Modeling Kit Interfacing Between LVDS and ECL ECLinPS Lite Translator ELT Family SPICE I/O Model Kit Using Wire-OR Ties in ECLinPS Designs The ECL Translator Guide Odd Number Counters Design Marking and Date Codes Termination of ECL Logic Devices
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MC10ELT25, MC100ELT25
PACKAGE DIMENSIONS
-X- A
8 5
SO-8 D SUFFIX PLASTIC SOIC PACKAGE CASE 751-07 ISSUE V
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
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MC10ELT25, MC100ELT25
PACKAGE DIMENSIONS
TSSOP-8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R-02 ISSUE A
8x
K REF 0.10 (0.004)
M
0.15 (0.006) T U
S 2X
TU
S
V
S
L/2
8
5
L
1 PIN 1 IDENT 4
B -U-
0.25 (0.010) M
0.15 (0.006) T U
S
A -V-
F DETAIL E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_
C 0.10 (0.004) -T- SEATING
PLANE
D
-W- G DETAIL E
DIM A B C D F G K L M
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MC10ELT25, MC100ELT25
Notes
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MC10ELT25, MC100ELT25
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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MC10ELT25/D

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